• GMII/MII Standard Interface with 3.3V/2.5V/1.8V Tolerant I/Os
• Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full) • On-Chip Termination Resistors for the Differential Pairs
• On-Chip LDO Controller to Support Single 3.3V Supply Operation
• Jumbo Frame Support Up to 16 KB
• 125 MHz Reference Clock Output
• Energy-Detect Power-Down Mode for Reduced Power Consumption When the Cable is Not Attached
• Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
• Programmable LED Outputs for Link, Activity, and Speed
• Baseline Wander Correction
• LinkMD TDR-based Cable Diagnostic to Identify Faulty Copper Cabling
• Parametric NAND Tree Support to Detect Faults Between Chip I/Os and Board
• Loopback Modes for Diagnostics
• Automatic MDI/MDI-X Crossover to Detect and Correct Pair Swap at All Speeds of Operation
• Automatic Detection and Correction of Pair Swaps, Pair Skew, and Pair Polarity
• MDC/MDIO Management Interface for PHY Register Configuration
• Interrupt Pin Option
• Power-Down and Power-Saving Modes
• Operating Voltages - Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (External FET or Regulator) - VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V - Transceiver (AVDDH): 3.3V or 2.5V (Commercial Temp.)
